1. Field of the Invention
The invention relates to a dual function injection type array readout device and circuit and to a dual function readout module.
2. Description of the Related Art
FIG. 1 shows a conventional infrared readout device having an infrared sensor D and a readout circuit 1, and disclosed in Longo, J. T., Cheung, D. T., Andrews, A. M., Wang, C. C., Tracy, J. M., “Infrared Focal Planes in Intrinsic Semiconductors,” Solid-State Circuits, IEEE Journal of, vol. 13, no. 1, pp. 139-158, February 1978.
A sense current exists when operating the infrared sensor D with reverse bias voltage, and the sense current includes a photoelectric current attributed to the infrared signal and a dark current that does not correspond to the infrared signal. In other words, the infrared sensor D creates a photoelectric current with a magnitude corresponding to intensity of the infrared signal detected thereby, and a dark current exists regardless of whether or not the infrared sensor D detects an infrared signal. The infrared sensor D is a photo-transmission diode D having an anode, and a cathode electrically coupled to a reference bias COM.
The readout circuit 1 includes a readout unit 2 and an ON/OFF control unit 22. The readout unit 2 includes a current-to-voltage converter 20 and a sample-and-hold device 21.
The current-to-voltage converter 20 includes a transistor M1, an integration capacitor CI, and an integration reset switch SIR. The current-to-voltage converter 20 is electrically coupled to the infrared sensor D to receive the sense current that is stored in the integration capacitor CI. The current-to-voltage converter 20 converts the sense current into an integration voltage that is directly proportional to the magnitude of the sense current.
The sample-and-hold device 21 is electrically coupled to the current-to-voltage converter 20. The sample-and-hold device 21 is controlled to sample and hold from the integration voltage to obtain an output voltage VOUT that is directly proportional to the magnitude of the sense current. The sample-and-hold device 21 includes a readout switch SSH, a sampling capacitor CSH, a sampling reset switch SRR, and an output switch MUL.
The transistor M1 includes a source electrically coupled to the anode of the photo-transmission diode D, a gate that receives a gate bias voltage VG, and a drain.
The integration capacitor CI includes a first terminal electrically coupled to and providing the integration voltage to the drain of the transistor M1, and a second terminal that receives a DC calibration potential Vadjust, which is used to adjust the initial value of the integration voltage.
The integration reset switch SIR is arranged parallel to the integration capacitor CI, and is operable to switch between conducting and non-conducting states. When the integration reset switch SIR conducts, the stored charge in the integration capacitor CI is cleared.
The readout switch SSH includes a first terminal electrically coupled to the drain of the transistor M1, and a second terminal, and is operable to switch between conducting and the non-conducting states.
The output switch MUL includes a first terminal electrically coupled to the second terminal of the readout switch SSH, and a second terminal providing an output voltage VOUT, and is operable to switch between conducting and the non-conducting states.
The sampling capacitor CSH includes a first terminal electrically coupled to the second terminal of the readout switch SSH, and a grounded second terminal.
The sampling reset switch SSR is arranged parallel to the sampling capacitor CSH, and is operable to switch between conducting and non-conducting states. When the sampling reset switch SSR conducts, the charge stored in the sampling capacitor CSH is cleared.
The ON/OFF control unit 22 is electrically coupled to the switches of the readout unit 2, and outputs multiple control signals to the corresponding switches to control operations of the switches in the conducting and non-conducting states. The operation of the readout unit 2 according to the control signals is described as follows:
The sense current generated by the infrared sensor D is injected, via the transistor M1, into the integration capacitor CI to perform the integration process and obtain the integration voltage. Prior to the integration process, the integration reset switch SIR is caused to conduct for some time to clear the charges inside the integration capacitor CI. After conducting the integration process for some time, the readout switch SSH is caused to conduct for some time to sample the integration voltage and store in the sampling capacitor CSH. The output switch MUL is then caused to conduct for some time so that the voltage at the first terminal of the sampling capacitor CSH is outputted as the output voltage VOUT. The sampling reset switch SSR is then caused to conduct for some time to clear the remaining charges from the sampling capacitor CSH. The above steps are repeated according to the control signals.
The conventional infrared readout device has the following drawbacks:
The magnitude of the dark current will vary with characteristics of the materials of the infrared sensor D. The magnitude of the dark current is influenced further by changes in the ambient temperature, background noise, and defects in the infrared sensor D. While the integration capacitor is fixed, the integration voltage may have a problem of over saturation when integrating due to excessively large dark current, and the integration voltage is thus not directly proportional to the magnitude of the sense current generated by the infrared sensor D, causing the readout of the output voltage VOUT to be incorrect.